Correspondence papers
S. Kashioka, M. Ejiri, and Y. Sakamoto: A Transistor Assembly System Utilizing Time-shared Visual Image Processing
Transaction of the IEEJ, Vol. C-96, No. 1, pp. 9-16, Jan. 1976 (in Japanese).
S. Kashioka, M. Ejiri, and Y. Sakamoto:A Transistor Wire-Bonding System Utilizing Multiple Local Pattern Matching Techniques
IEEE Trans. SMC, Vol. SMC-6, No. 8, pp. 562-570, Aug. 1976.
M. Mese, T. Miyatake, S. Kashioka, M. Ejiri, I. Yamazaki, and T. Hamada:An Automatic Recognition Technique for LSI Assembly
Proc. 5th IJCAI, pp. 685-693, 1977.
Related papers
[1] Y. Shima, S. Kashioka, and M. Ejiri
A Fast Algorithm for Template Pattern Matching Based on Probability of Occurrence of Sub-Patterns
Transaction of the IEICE, Vol.J68-D, No.2, pp.161-168, Feb. 1985 (in Japanese).
[2] S. Kashioka, Y. Shima, and M. Ejiri
Automatic Template Selection Technique for the Local Pattern Matching Method
Transaction of the IEICE, Vol.J 68-D, No. 5, pp. 1103-1110, May 1985 (in Japanese).
[3] Y. Sako, T. Miyatake, Y. Shima, S. Kashioka, and M. Ejiri
A Position Recognition Algorithm Based on the Distribution of Characteristic Patterns
Transaction of the IEICE, Vol. J71-D, No. 7, pp. 1258-1266, July 1988 (in Japanese).
[4] H. Sakou, T. Miyatake, S. Kashioka, and M. Ejiri
A Position Recognition Algorithm for Semiconductor Alignment Based on Structural Pattern
Matching, IEEE Trans. ASSP, Vol. 37, No. 12, pp.2148-2157, Dec. 1989.